Apparatus system and method for identification of memory

ABSTRACT

A system and method of identifying a memory includes detecting defects in regions of the memory, comparing the detected defects with defects contained in a previously-created defect map associated with the memory and stored in another memory of a device accessing the memory, confirming the identity of the memory where a result of the comparison indicates the detected defects match defects contained in the previously-created defect map; and denying the identity of the memory where the result of the comparison indicates the detected defects do not match the defects contained in the previously-created defect map.

CLAIM TO PRIORITY UNDER 35 U.S.C. §120

The present Application is a continuation of and claims the benefit ofU.S. Pat. No. 8,572,440 filed on Nov. 15, 2010, entitled, “SYSTEM ANDMETHOD FOR MANAGING INFORMATION STORED IN SEMICONDUCTORS,” and U.S.patent application Ser. No. 13/974,473 filed on Aug. 23, 2013, entitled“SYSTEM AND METHOD FOR IDENTIFICATION OF MEMORY,” both of which areassigned to the assignee hereof, and expressly incorporated herein byreference in their entirety.

FIELD

The present disclosure relates generally to computer systems andinformation handling systems, and, more particularly, to a system andmethod for employing a map of functional error or inconsistency of asemiconductor device to govern the use of data stored therein by acomputer system or information handling system

DESCRIPTION OF THE RELATED ART

As the value and use of information continues to increase, individualsand businesses seek additional ways to manage and secure storedinformation. One option available to these users is an informationhandling system. An information handling system generally processes,compiles, stores, and/or communicates information or data for business,personal, or other purposes thereby allowing users to take advantage ofthe value of the information. Because technology and informationhandling needs and requirements vary between different users orapplications, information handling systems may vary with respect to thetype of information handled; the methods for handling the information;the methods for processing, storing or communicating the information;the amount of information processed, stored, or communicated; and thespeed and efficiency with which the information is processed, stored, orcommunicated. The variations in information handling systems allow forinformation handling systems to be general or configured for a specificuser or specific use such as financial transaction processing, airlinereservations, enterprise data storage, or global communications. Inaddition, information handling systems may include or comprise a varietyof hardware and software components that may be configured to process,store, and communicate information and may include one or more computersystems, data storage systems, and networking systems.

A computing system will typically include some type of informationstorage medium. In recent computers, the amount of memory comprised bythe information handling system may be on the order of gigabytes. Asmemory size increases, there is an increased likelihood that part of thememory will either be manufactured defective or become defective overtime. These systems may also include cryptographic systems, which areconstructed with software, hardware or a combination of both.

Numerous cryptographic processes are well defined in the art and areknown to generally be strong mechanisms which generally rely on the useof passwords and/or keys. These systems are often only as secure as thevigilance of their users and can create undue burden on users. Moreover,such users commonly disable or defeat the security provisions for theirconvenience, or for illicit purposes.

As computing systems continue to evolve and computer technologyadvances, the significance and value of information also is advancing.Hence there is a need for secure data repositories which allow readyaccess to data stored therein while preventing unauthorized copying ordistribution has become a critical need.

While systems for securing financial or sensitive information access insolid-state devices such as semiconductor memory cards are wellrepresented in the prior art, the unique issue of securing data fromduplication or illicit use is becoming a pervasive problem. Largequantities of data don't simply represent value, but are instead theactual value

A semiconductor memory card typically stores data in solid-state memorysuch as a Non Volatile Memory (NVM). After information is written to thesemiconductor memory, security becomes vital. Long-term, unsupervisedaccess to the memory lends itself to attacks of all forms to attempt todisconnect the information from the physical memory. It is possible fora skilled attacker to retrieve numerical information from asemiconductor memory card through probing of the internal components ofthe device, or through other unauthorized means. If card security isprovided only through numerical means, such as numerical authenticators,or cryptographic processing keys, it is possible to create a counterfeitcard which contains information duplicated from a legitimate card.

Some techniques offer data access security through the use of datarelated to physical characteristics of the storage media. These systemsrely on precise measurement of solid state media processcharacteristics. Examples of these include variations in the remnantcharge of EEPROM's, or variations in row/column addressing circuits.These and other characteristics have been used for authentication whenthe memory is presented, and the authenticating characteristics aremeasured. Such techniques are described in detail in Fernandez (U.S.Pat. No. 5,644,636).

The critical issue which cannot be addressed by the prior art areapplications where data security is not simply shifted to attacks on thereader mechanisms and where data must not be duplicated or separatedeven by trusted and/or authorized users.

SUMMARY

In accordance with the present disclosure, an aspect of the inventiondiscloses a method for securely storing and using information whereby asemiconductor is tested for inconsistencies and detected functionalimperfections are stored in a functional defect map and used in part tosecure, unsecure or govern use of data.

An aspect of the present invention significantly increases the securityand rights management of the data stored in digital form by allowing theuse of semiconductor components which not only bare their own uniqueindelible characteristics but integrate those characteristics (bothstatic and transient) into the stored data.

In an aspect of the present invention, utilization of a semiconductorsunique fabricated characteristics in this way allows an informationhandling system to exclusively couple data to the semiconductorcomponent (or components) used to store, enable application of the dataas well as impede copying of the stored data held in the semiconductorcomponent, the memory component can be moved from one system to anotherwhile retaining data security. In this way, no burden is placed on thereader and in fact these systems allow for unsecured direct bus access.The importance of this improvement is magnified as semiconductors aregrowing to be a dominant media for mass storage.

An aspect of the present invention allows the system to maintain normaloperations despite significant data security. By minimizing the impactof security processes a system and method in accordance with the presentinvention can render data stored in semiconductors useful yetuncopyable.

An aspect of the present invention greatly reduces the system and usersburden associated with data rights management.

According to an aspect of the invention, a method of identifying amemory, includes detecting defects in regions of the memory; comparingthe detected defects with defects contained in a previously-createddefect map associated with the memory and stored in another memory of adevice accessing the memory; confirming the identity of the memory wherea result of the comparison indicates the detected defects match defectscontained in the previously-created defect map; and denying the identityof the memory where the result of the comparison indicates the detecteddefects do not match the defects contained in the previously-createddefect map.

According to an aspect of the invention, the method further includesallowing a data exchange between the device and the memory where theidentity of the memory is confirmed, and preventing the data exchangebetween the device and the memory where the identity of the memory isdenied.

According to an aspect of the invention, the detecting the defectscomprises detecting the defects in selected regions of the memory, andlocations of the selected regions are pre-determined.

According to an aspect of the invention, the detected defects matchdefects contained in the previously-created defect map where adifference between the detected defects and the defects contained in thepreviously-created defect map is within a predetermined error rate.

According to an aspect of the invention, when there is a differencebetween the detected defects and the defects contained in thepreviously-created defect map, the method further includes performing asecondary authentication of the memory to confirm the identity of thememory, wherein the identity of the memory is confirmed where thesecondary authentication is successful.

According to an aspect of the invention, the method further includesstoring the detected defects in the another memory as a newly-createddefect map where the secondary authentication is successfully performed.

According to an aspect of the invention, the method further includesstoring the detected defects in the another memory as a newly-createddefect map associated with the memory.

According to an aspect of the invention, the method further includesdetermining that the memory is not a counterfeit having counterfeit dataand allowing a data exchange between the device and the memory where theidentity of the memory is confirmed, and determining that the memory isa counterfeit having counterfeit data and preventing the data exchangebetween the device and the memory where the identity of the memory isdenied.

According to an aspect of the invention, the detecting the defectscomprises performing a normal read process of selected cells todetermine which of the selected cells of the memory were written as alogical first state but are read as a logical second state to determinewhich cells have an error, and comparing the cells having the error withthe defect map.

According to an aspect of the invention, the method further includeswriting data in a predetermined pattern of the logical first and secondstates to the selected cells prior to the detecting the defects.

According to an aspect of the invention, the previously-created defectmap comprises a defect list of the memory used in defect management ofthe memory, the detecting the defects comprises writing data in apredetermined pattern to the memory in regions included on the defectlist, and the comparing comprises comparing the detected defects withthe defect list stored in the another memory of the device.

According to an aspect of the invention, the previously-created defectmap is stored encrypted, and the comparing further comprises decryptingthe encrypted previously-created defect map and comparing the decryptedpreviously-created defect map with the detected defects.

According to an aspect of the invention, the memory comprises at leastone of a semiconductor memory, a magnetic memory, an optical memory, orcombinations thereof.

According to an aspect of the invention, a method of providingidentification of a memory includes detecting defects in regions of thememory; and storing the detected defects as a defect map associated withthe memory in another memory of a device accessing the memory so as touniquely identify the memory to the device.

According to an aspect of the invention, the method further includes,after reconnecting the memory to the device, confirming an identity ofthe memory by again detecting defects in regions of the memory,comparing the again detected defects with the stored defect map,confirming the identify of the memory where a result of the comparisonindicates the again detected defects match defects contained in thestored defect map, and denying the identity of the memory where theresult of the comparison indicates the again detected defects do notmatch the defects contained in the stored defect map.

According to an aspect of the invention, the method further includesallowing a data exchange between the device and the memory where theidentity of the memory is confirmed, and preventing the data exchangebetween the device and the memory where the identity of the memory isdenied.

According to an aspect of the invention, the detecting the defectscomprises detecting the defects in selected regions of the memory, andlocations of the selected regions are pre-determined.

According to an aspect of the invention, the again detected defectsmatch defects contained in the stored defect map where a differencebetween the again detected defects and the defects contained in thestored defect map is within a predetermined error rate.

According to an aspect of the invention, the method further includes,when there is a difference between the again detected defects anddefects contained in the stored defect map, performing a secondaryauthentication of the memory to confirm the identity of the memory,wherein the identity of the memory is confirmed where the secondaryauthentication is successful.

According to an aspect of the invention, the method further includesstoring the again detected defects in the another memory as an updateddefect map after the secondary authentication is successfully performed.

According to an aspect of the invention, the method further includesstoring the again detected defects in the another memory as anewly-created defect map associated with the memory.

According to an aspect of the invention, the method further includesdetermining that the memory is not a counterfeit having counterfeit dataand allowing a data exchange between the device and the memory where theidentity of the memory is confirmed, and determining that the memory isa counterfeit having counterfeit data and preventing the data exchangebetween the device and the memory where the identity of the memory isdenied.

According to an aspect of the invention, the detecting the defectscomprises performing a normal read process of selected cells todetermine which of the selected cells of the memory were written as alogical first state but are read as a logical second state to determinewhich cells have an error, and comparing the cells having the error withthe stored defect map.

According to an aspect of the invention, the method further includeswriting data in a predetermined pattern of the logical first and secondstates to the selected cells prior to the again detecting the defects.

According to an aspect of the invention, the stored defect map comprisesa defect list of the memory used in defect management of the memory, andthe detecting the defects comprises reading the defect list from thememory.

According to an aspect of the invention, the stored defect map comprisesa defect list of the memory used in defect management of the memory, thedetecting the defects comprises reading the defect list from a memory,the again detecting the defects comprises writing data in apredetermined pattern to the memory in regions included on the defectlist, and the comparing comprises comparing the again detected defectswith the defect list stored in the another memory of the device.

According to an aspect of the invention, the method further includesencrypting the defect list prior to storing the defect list.

According to an aspect of the invention, an information handling systemincludes: a memory which stores a defect map associated with anothermemory connectable to the information handling system; and a processorwhich, when the another memory is connected to the information handlingsystem, detects defects in regions of the another memory, compares thedetected defects with defects contained in the stored defect map,confirms the identity of the another memory where a result of thecomparison indicates the detected defects match defects contained in thestored defect map, and denies the identity of the memory where theresult of the comparison indicates the detected defects do not match thedefects contained in the stored defect map.

According to an aspect of the invention, the processor allows a dataexchange between the information handling system and the another memorywhere the identity of the another memory is confirmed, and prevents thedata exchange between the information handling system and the anothermemory where the identity of the another memory is denied.

According to an aspect of the invention, the processor detects thedefects in selected regions of the another memory, and locations of theselected regions are pre-determined.

According to an aspect of the invention, the processor confirms theidentity of the another memory when a difference between the detecteddefects and the defects contained in the stored defect map is within apredetermined error rate.

According to an aspect of the invention, further comprising, when thedetected defects do not match defects contained in the stored defectmap, the processor performs a secondary authentication of the anothermemory to confirm the identity of the another memory.

According to an aspect of the invention, the processor stores thedetected defects in the memory as a newly-created defect map where thesecondary authentication is successfully performed.

According to an aspect of the invention, the processor stores thedetected defects in the memory as a newly-created defect map associatedwith the another memory.

According to an aspect of the invention, the processor furtherdetermines that the another memory is not a counterfeit havingcounterfeit data and allows a data exchange between the informationhandling system and the another memory where the identity of the anothermemory is confirmed, and determines that the another memory is acounterfeit having counterfeit data and prevents the data exchangebetween the information handling system and the another memory where theidentity of the another memory is denied.

According to an aspect of the invention, the processor detects thedefects while performing a normal read process of selected cells todetermine which of the selected cells of the another memory were writtenas a logical first state but are read as a logical second state todetermine which cells have an error, and comparing the cells having theerror with the defect map.

According to an aspect of the invention, the processor writes data in apredetermined pattern of the logical first and second states to theselected cells prior to the detecting the defects.

According to an aspect of the invention, the stored defect map comprisesa defect list of the another memory used in defect management of theanother memory which the processor copied and stored in the memory, andthe processor detects the defects by writing data in a predeterminedpattern to the another memory in regions included on the defect list,and compares the detected defects with the defect list stored in thememory.

According to an aspect of the invention, the processor encrypts thestored defect map and decrypts the encrypted defect map to perform thecomparison.

According to an aspect of the invention, the another memory comprises atleast one of a semiconductor memory, a magnetic memory, an opticalmemory, or combinations thereof.

According to an aspect of the invention, the processor performs thecomparison when the processor detects that the another memory hasre-attached to the information handling system after being detached fromthe information handling system.

According to an aspect of the invention, the processor performs thecomparison when the processor detects that the another memory hasreestablished a network connection to the information handling systemafter losing the network connection with the information handlingsystem.

According to an aspect of the invention, an information handling systemincludes: a memory; and a processor which, when another memory isconnected to the information handling system, detects defects in regionsof the another memory, and stores the detected defects as a defect mapassociated with the another memory in the memory so as to uniquelyidentify the another memory to the information handling system.

According to an aspect of the invention, the processor, after theinformation handling system reconnects to the another memory, confirmsan identity of the another memory by again detecting defects in regionsof the another memory, comparing the again detected defects with thestored defect map, confirming the identify of the another memory where aresult of the comparison indicates the again detected defects matchdefects contained in the stored defect map, and denying the identity ofthe another memory where the result of the comparison indicates theagain detected defects do not match the defects contained in the storeddefect map.

According to an aspect of the invention, the processor allows a dataexchange between the information handling system and the another memorywhere the identity of the another memory is confirmed, and prevents thedata exchange between the information handling system and the anothermemory where the identity of the another memory is denied.

According to an aspect of the invention, the processor detects thedefects in selected regions of the another memory, and locations of theselected regions are pre-determined.

According to an aspect of the invention, the processor confirms that theagain detected defects match defects contained in the stored defect mapwhere a difference between the again detected defects and the defectscontained in the stored defect map is within a predetermined error rate.

According to an aspect of the invention, when the result of thecomparison indicates the again detected defects do not match defectscontained in the stored defect map, the processor performs a secondaryauthentication of the another memory to confirm the identity of theanother memory.

According to an aspect of the invention, the processor further storesthe again detected defects in the memory as an updated defect map wherethe secondary authentication is successfully performed.

According to an aspect of the invention, the processor further storesthe again detected defects in the memory as a newly-created defect mapassociated with the another memory.

According to an aspect of the invention, the processor determines thatthe another memory is not a counterfeit having counterfeit data andallows a data exchange between the information handling system and theanother memory where the identity of the another memory is confirmed,and determines that the another memory is a counterfeit havingcounterfeit data and prevents the data exchange between the informationhandling system and the another memory where the identity of the anothermemory is denied.

According to an aspect of the invention, the processor detects thedefects by performing a normal read process of selected cells todetermine which of the selected cells of the another memory were writtenas a logical first state but are read as a logical second state todetermine which cells have an error, and comparing the cells having theerror with the defect map.

According to an aspect of the invention, the processor writes data in apredetermined pattern of the logical first and second states to theselected cells prior to the detecting the defects.

According to an aspect of the invention, the stored defect map comprisesa defect list of the another memory used in defect management of theanother memory which the processor copied and stored in the memory.

According to an aspect of the invention, the stored defect map comprisesa defect list of the another memory used in defect management of theanother memory which the processor copied and stored in the memory, andthe processor detects the defects by writing data in a predeterminedpattern to the another memory in regions included on the defect list,and compares the detected defects with the defect list stored in thememory.

According to an aspect of the invention, the processor encrypts thedefect list prior to storing the defect list in the memory.

According to an aspect of the invention, a computer readable medium isencoded with processing instructions for implementing the method ofaspects of the invention using one or more processors.

Additional aspects and/or advantages of the invention will be set forthin part in the description which follows and, in part, will be obviousfrom the description, or may be learned by practice of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and advantages of the invention will becomeapparent and more readily appreciated from the following description ofthe embodiments, taken in conjunction with the accompanying drawings ofwhich:

FIG. 1 illustrates a typical information handling system adapted tomanage data use according to an embodiment of the present invention;

FIG. 2 illustrates a process for writing data to semiconductor memorycells according to an embodiment of the present invention;

FIG. 3 illustrates a process for reading data from semiconductor memorycells according an embodiment of to the present invention;

FIG. 4 illustrates an alternative process for reading data fromsemiconductor memory cells according to an embodiment of the presentinvention;

FIG. 5 illustrates a process for generating a reference fingerprint ofdata stored in semiconductor memory cells according an embodiment of tothe present invention; and

FIG. 6 illustrates a process for authenticating data stored insemiconductor memory cells by employing a reference fingerprint inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION

Reference will now be made in detail to the present embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to the like elementsthroughout. The embodiments are described below in order to explain thepresent invention by referring to the figures.

FIG. 1 shows an information handling system 100 according to an aspectof the invention. The shown information handling system 100 may includeany instrumentality or aggregate of instrumentalities operable tocompute, classify, process, transmit, receive, retrieve, originate,switch, store, display, manifest, detect, record, reproduce, handle, orutilize any form of information, intelligence, or data for business,scientific, control, or other purposes. For example, the informationhandling system 100 may be a personal computer, a network storagedevice, a tablet, a netbook, a server, a personal digital assistant, asmart phone, a personal media player, or any other suitable device andmay vary in size, shape, performance, functionality, and price.

While not required in all aspects, the shown information handling system100 includes a random access memory (RAM) 160, one or more processingresources such as a central processing unit (CPU) 110 or hardware orsoftware control logic, a ROM, and/or other types of nonvolatile memory(NVM) 180.

While not required in all aspects, the shown information handling system100 includes one or more disk drives such as a hard drive 190, one ormore network ports for communication with external devices as well asvarious input and output (1/0) devices, such as a keyboard 150, and amouse 155. The information handling system 100 may also include one ormore buses operable to transmit communications between the varioushardware components, and may also include or be connectable to a videodisplay, speaker, and/or microphone to facilitate communication with auser of the information handling system 100.

The CPU 110 is communicatively coupled to a memory controller hub (MCH)or north bridge 120. The memory controller hub 120 is coupled to the RAM160 and a graphics processing unit (GPU) 170. The memory controller hub120 is also coupled to an 1/0 controller hub or south bridge 130. The1/0 hub 130 is coupled to storage elements of the information handlingsystem 100. As shown, the storage elements include the NVM 180, and thehard drive 190 of the computer system. While not required in allaspects, the NVM 180 can be a flash ROM for the Basic Input/OutputSystem (BIOS) of the information handling system 100.

While not required in all aspects, the 1/0 hub 130 is also coupled to aSuper 1/0 chip 140. The shown 1/0 chip 140 is coupled to many of the 1/0ports of the information handling system 100, including the keyboard150, mouse 155, parallel ports 145, and a memory drive 185. However, itis understood that the ports can be connected to other elements inaddition to or instead of the shown keyboard 150, mouse 155, andparallel ports 145, such as a touch screen display, a printer ormultifunction device, a display, speakers, a microphone, an externaldrive or other like peripheral.

The memory drive 185 is connectable to the information handling system100. The memory 185 can be a semiconductor memory, an optical memory,and/or a magnetic memory. The memory 185 can be a rewritable memory, awrite once memory, and/or a read only memory. The memory drive 185receives the information handling system 100 data, and transfers thedata with respect to the information handling system 100. The memorydrive 185 can be a read only drive, and can be a read and write drivedepending on the type of information handling system 100. While shown asbeing connected through the Super 1/0 chip 140, and is understood thatthe memory drive 185 could be connected to the 1/0 hub 130 in additionto or instead of using the Super 1/0 chip 140. While shown as detachablefrom the information handling system 100, it is understood that thememory 185 could be not detachable in aspects of the invention. Further,in aspects of the invention, the memory drive 185 can be connected tothe information handling system 100 through a network, whereby theinformation handling system 100 could be disconnected from the memorydrive 185, when the information handling system 100 is powered off, orwhen the information handling system 100 purposely disconnects from thememory drive 185.

The CPU 110 identifies the memory 185 using a reference map stored in amemory (such as the NVM 180) by comparing defects in the memory 185 andthose in the reference map according to aspects of the invention, anddetermines whether the memory 185 is counterfeit or known according toaspects of the invention described below. A result of the identificationcan be for the CPU 110 to allow a data transfer with respect to thememory 185 where the memory 185 is found to be known, and prevent thedata transfer with respect to the memory 185 where the memory 185 isfound to be counterfeit. In other aspects, the information handlingsystem 100 can inform a user (such as through a pop-up window on adisplay, logging of the alert in an event monitor, or an audio alertplayed through speakers) where the memory 185 is found to becounterfeit. In other aspects, where the user is informed of thecounterfeit nature of the memory 185, the user can permit the datatransfer with respect to the memory 185.

FIG. 2 presents an exemplary memory space 200. As such, the exemplarymemory space 200 has defective regions 210, 220, 230. As shown, eachdefective region 210, 220, 230 has non-defective sectors, and at leastone defective sector (shown with an X). The exemplary memory space 200may be part of a flash memory, which can be a removable memory such asthat in the detachable memory 185 shown in FIG. 1, or any othercomponent capable of being addressed as memory. To the extent thesedefective regions 210, 220, 230are in existence at the time ofmanufacture of the memory component, information regarding the locationof the defective memory regions 210, 220, 230 may be stored in a secureaddress in the memory 200 during manufacture. Specifically, the memorycomponent is tested at the time of manufacture either externally or viabuilt in self test (BIST) methods, and any information regarding thelocation of defective memory is stored in a secure nonvolatile addressof the device. An example of such tests and defect management as used inoptical media is described in 120 mm DVD Rewritable Disk(DVD-RAM),Standard ECMA-272 (2nd Edition—June 1999), the disclosure of which isincorporated by reference.

Such defect information can be stored on the hard drive 190 and/or thedetachable memory 185 of FIG. 1 for use in defect management, such as ina primary defect list (POL). Moreover, where errors occur after use ofthe memory 185 of FIG. 1, such additional defects can also be stored onthe memory, such as in a secondary defect list (SOL). In this manner,the processor using the memory, such as the CPU 110 of FIG. 1, is ableto utilize the memory and avoid defective locations. Further, since thedefect list keeps changing as new defects appear, aspects of theinvention use these changes in defect locations to work to increase thesecurity of the data contained on the memory.

FIG. 3 illustrates a process 300 for writing data according to anembodiment of the present invention with reference to a semiconductormemory. The data written can then be used to determine patterns ofmemory cells static, dynamic or transient anomalies of thesemiconducting device to which the data has been written. The process ofdetermining the patterns of static, dynamic and transient error isdiscussed below in connection with FIG. 4. The process may suitably beemployed with a data storage device such as the information handlingsystem 100, employing a processor 110, the detachable memory 185 anddata, address and control buses similar to those illustrated in FIG. 1above. While illustrated in the presently preferred context of theprocessor 110 communicating with the detachable memory 185, it will berecognized that the techniques of the present invention may be employedwith any semiconducting device, and other types of storage.

At step 310, a list of selected memory cells to which data is to bewritten is created. While not required in all aspects, the list ofselected memory cells need not be all of the memory cells used in thememory array, but instead are memory cells in predetermined locationsacross the memory array. Thus, as compared to defect managementtechniques which evaluate and account for defects in the memory array asa whole, only the selected memory cells are used for purposes ofidentification as will be discussed in detail below. However, it isunderstood that aspects of the invention can utilize all of the memorycells as opposed to only selected ones.

At step 320, a value of “1” or “0” is associated with each memory cellof the list, as the data to be written to that memory cell. At step 320,the first entry in the list is examined to determine the destinationaddress where the data is to be written. At step 330, the destinationaddress is placed on the address bus. At step 340, data is placed on thedata bus. At step 340, the control bus is set to enable a writeoperation. At step 350, the data is written to the destination address.At step 360, the entry for which the data was written is removed fromthe list. At step 370, the list is examined to determine if it is empty.If the list is not empty, the process proceeds to step 380 and the nextentry on the list is examined to determine the destination address wheredata is to be written. The process then returns to step 330. If the listis empty, the process terminates at step 390. This method as describedin FIG. 3 is offered for illustrative purposed it will be recognized byone of ordinary skill in the art that Built in Self Test (BIST) may alsobe employed in the determination of static, dynamic and transient errorsin a semiconducting memory.

FIG. 4 illustrates a process 400 for obtaining and storing datarepresenting functional errors in selected programmed memory cells of amemory array according to an embodiment the present invention. At step410, a list of selected memory cells is established. The list may be thesame as the list used in step 310. Alternately, the list can be forregions having defective sectors on the primary defect list (POL) orsecondary defect list (SOL) read from the memory array and is thuspotentially variable each time the memory array is used.

At step 420, a read operation is performed for the selected memorycells. At step 430, data from each of the selected cells which was readin the read operation of step 420 is verified to have the same or adifferent logical value than the logical value written in step 350. Byway of example, where the data contained at the selected cell isassigned the level of trapped charges indicated by the threshold, and avalue representing the assigned level of trapped charges is stored foreach cell. A cell which contains a logical “1” but which was read as alogical “0” in the read operation of step 420 or a cell which contains alogical “0” but which was read as a logical “1” in the read operation ofstep 420. At step 440, each of the cells having a variation (e.g., whichwas written as a “0” and recognized as a “1,” and which was written as a“1” and recognized as a “0” is removed from the list of selected memorycells. At step 450, the list of selected cells is examined to determineif it is empty. If the list is not empty, the process proceeds to step420. If the list is empty, the process proceeds to step 460. At step460, the stored representations of the error map for the selected cellsare assembled to create a reference fingerprint which can be used toidentify the memory array.

The reference fingerprint is then stored in the device which isaccessing the memory array. By way of example, the reference fingerprintcan be stored in hard drive 190 of the system 100 of FIG. 1, and thememory array could be the memory 185 of FIG. 1. Thus, in subsequent usesof the memory array whose reference fingerprint is determined, theidentity of the memory array can be verified by the device using thereference fingerprint even where the memory array has been detached fromthe device. Where the identity is verified, it is determined that thedata on the memory array is not a duplicate or from a counterfeit cardwhich contains information duplicated from a legitimate card having thereference fingerprint.

FIG. 5 illustrates a process 500 for writing data to and reading datafrom selected cells of a semiconductor memory array in order to generatea reference map comprising data representative of “stuck at”, retentionand leaking defects (corresponding to the static, dynamic and transientdefects) in the array according to an aspect of the invention. Thereference map is generated after data is written to the array. At step510, data is written to selected cells of the memory array, such asthrough using the process illustrated in FIG. 3. At step 520, thedefects of the selected cells are determined, such as through using theprocess of FIG. 4. At step 530, representations of error location andtypes are used to create a reference map which uniquely identifies thesemiconducting device which was written. Alternatively, the referencefingerprint may comprise a linear feedback shift register to compact theerror locations rather than storing the numerical representations oflocations and types of error obtained in step 520. At step 540, therepresentations of the reference defect locations are stored for use insubsequently managing data access to subsequent data stored in thesemiconductor, and to identify the memory array even where the memoryarray has been removed from the device as compared to a duplicate of thememory array.

While not required in all aspects, the reference defect locations may beused as functional memory to store data during normal use. Thus, datamanagement information in a chosen location within the memory array, oralternatively may be passed to an output of the memory device forexternal storage may offer session keying and memory patterning which isonly replicable by the semiconductor itself without sacrificing storagespace otherwise usable by the memory device. As such, the reference mapis unique to the memory device and is usable to identify thesemiconductor memory when subsequently used by the device.

Moreover, while not required in all aspects, where the reference map isupdated for errors which grow during use in addition to errors foundduring manufacture, the uniqueness of the reference map increases sincethe fingerprint has more unique data points.

While not required in all aspects, the reference defect locations and/orreference map may be encrypted before storage in the device.

Also, while not required in all aspects, the manufacturer of the memoryarray could introduce or allow for higher error rates on the memoryarray, thereby improving the number of defective locations and theuniqueness of the reference map. As such, while the memory array wouldhave a reduced storage, the memory array would also be more secure andidentifiable according to aspects of the invention. A further advantageis that the manufacturer costs could be reduced since, with a highererror rate being allowed, fewer memory arrays would be deemedunacceptable and the manufacturing tolerances could be loosened to allowmore of the defective locations to be introduced into the resultingmemory array. By way of example, the lessening of manufacturingtolerances to purposefully introduce errors randomly in semiconductor,magnetic or optical would provide a greater abundance of intermittenterror (i.e., while one can over voltage a memory location to force it toground or power, but it cannot be made intermittent where it loses itsdata over a couple of clock cycles). For low cost magnetic equivalents,such introduction would equate to inadequate distribution of the ferricmaterial in a magnetic strip and disk drives would be more likesemiconductors (i.e. process contamination, etc.). Optical memory couldallow bits being inscribed onto the aluminum in a loose fashion suchthat a segment of information (likely in a known place) will be readdifferently at times as the tolerance of the reader has been disregardedto create interspersed errors. However, other methods can be used tointroduce or allow such errors at the manufacturing stage in otheraspects of the invention.

FIG. 6 illustrates a process 600 for using data stored in a memorydevice according to an aspect of the present invention. At step 610, theselected memory cells from which the reference defect locations wascreated are read using a normal read process to determine which cellswere written as logical “1s” and which cells were written as logical“Os”. At step 610, the selected memory cells from which the referencedefect locations were created are read which if duplicated directly willyield a static, dynamic or transient error thereby corrupting local dataintegrity unless conditionally filtered by the reference map. At step620, the read result from step 610 is compared with the stored referencemap of the device. While not required in all aspects, the reference mapcan be generated by the device in a prior session of using the memorydevice. At step 630, transient data variations are added into the staticreference map thus creating the active reference map. Alternately, thereference map can be retrieved from an external location (such as aserver), such as where a reader retrieves an identification of thememory device (such as from the memory device), sends the retrievedidentification to the external location, retrieves the reference mapfrom the external location, and stores the reference map so as toauthenticate the memory device.

Variations are detected at step 620. If there are variations, it isdetermined that the memory array is not recognized by the device, anddata access is denied at step 640. If there are no variations, it isdetermined that the memory array is recognized by the device, and dataaccess is allowed at step 640. In this manner, a mechanism forrestricting access by and to the memory array is provided.

While not required in all aspects, as additional defects can begenerated after the reference map was stored in the device, it isunderstood that the device could allow access where a statisticallysmall variation exists at step 620. Where the variation is small, thedevice could automatically allow the access or could request some formof secondary authentication (such as from a user) and allow the accesswhere the secondary authentication is satisfied. Where there is thisaccess after a small variation, aspects of the invention allow thedevice to revise the reference map stored in the device using the newlist of defective memory cells.

According to an aspect of the invention, after the memory array isrecognized by the device, and data access is allowed at step 640, oncompletion of a data transfer operation, the reference map is updated.By way of example, after data is written to the memory array, averification operation is performed to confirm that the data is writtencorrectly. Where the verification operation detects an error in thewritten data, the defective location is added to the reference map.Similarly, where a read operation is performed and a location cannot beread but was not previously found to be defective, the defectivelocation is added to the reference map. The updated reference map isstored in the device for a next usage of the memory array in the device.In this manner, the reference map is updated to account for defectswhich occur during each data transfer session, which further improvesthe identification of the memory array by the device.

While not required in all aspects, it is understood that additionalsecurity measures could be used in addition to the variation detectionin order to ensure that the identity of the memory array is proper andthe data on the memory array is not counterfeited.

While described in terms of using defects on semiconductor memory, it isunderstood that aspects of the invention could be used with defects onother types of memories, including optical memory such as Blu-ray,holographic and DVD memory, and magnetic memory such as hard drives.Further, while described in terms of creating a reference map includingreference defect locations, aspects could also use primary and/orsecondary defect lists used in defect management of the memory and whichcould be encrypted and stored on the reading/writing device and laterused to verify if the same memory has been reconnected to thereading/writing device. Lastly, while described in terms of thereference map, other aspects of the invention could store a disk imagewith the known reference defect locations, and the disk image could becompared with the memory when reconnected to determine if the defectlocations have changed.

While not required in all aspects, elements of the present invention canbe implemented using computer software and/or firmware encoded on acomputer readable medium and executed by one or more processors and/orcomputers.

Although a few embodiments of the present invention have been shown anddescribed, it would be appreciated by those skilled in the art thatchanges may be made in this embodiment without departing from theprinciples and spirit of the invention, the scope of which is defined inthe claims and their equivalents.

What is claimed is:
 1. An apparatus for uniquely identifying a memory,comprising: an information handling system; a first memory; acommunication port; and a processor adapted to communicatively couplewith a second memory, to detect defects in regions of the second memory,to store the detected defects as a defect map, to associate the defectmap with the second memory, to store the associated defect map in thefirst memory, to use the stored associated defect map to subsequentlyuniquely identify the second memory, and to use the uniqueidentification for security purposes between the second memory and thefirst memory.
 2. The apparatus of claim 1, wherein the processor isadapted to detect the defects in selected regions of the second memory,and locations of the selected regions are pre-determined.
 3. Theapparatus of claim 1, wherein the stored defect map comprises a defectlist of the second memory used in defect management of the second memorywhich the processor is adapted to copy and store in the second memory.4. The apparatus of claim 1, wherein the processor is adapted to encryptthe defect list prior to storing the defect list in the first memory. 5.The apparatus of claim 1, wherein the second memory is one of asemiconductor memory, a magnetic memory, an optical memory, or acombination thereof.
 6. The apparatus of claim 1, further comprising:allowing a data exchange between the information handling system and thesecond memory where the identity of the second memory is confirmed; andpreventing the data exchange between the information handling system andthe second memory where the identity of the second memory is denied. 7.The apparatus of claim 1, wherein the processor is adapted to detectdefects in regions of the second memory by writing a logical state tothe second memory, and reading a different logical state than what waswritten.
 8. The apparatus of claim 1, wherein the processor is adaptedto detect new defects in regions of the second memory and store anupdated defect map.
 9. The apparatus of claim 1, wherein the defects inregions of the second memory are functional imperfections.